Interactive teaching companion

How LLM inference really works

An animated, click-through companion to IOP Systems' Inference Infrastructure series — eleven modules taking you from a single attention head all the way to a production serving stack. Every concept is a hands-on animation you can play, pause, and step through at your own pace.

▶ / ⏸ play & pause ◂ ▸ step a mechanism one move at a time replay speed slider on auto-play figures
tokens / requests model weights KV cache compute / GPU work attention scores memory / HBM stalls / waste
Core modules
01 · Foundations

LLMs & Transformers

Embeddings, attention (Q·Kᵀ→softmax→V), multi-head, MHA/MQA/GQA/MLA, and Mixture-of-Experts.

5 figures · step + auto
KV cache grows ↑
02 · Foundations

Inference & the KV Cache

Prefill vs decode, why recomputing K/V is wasteful, and how the cache trades memory for speed.

4 figures · step + auto
GPU0 GPU1
03 · Scaling out

Sharding a Model

Pipeline parallelism & bubbles, tensor parallelism with all-reduce, and expert parallelism.

4 figures · step + auto
idle slot →
04 · Scaling out

Batching, Scheduling & Paging

Static vs continuous batching (Orca) and PagedAttention's block table for the KV cache.

4 figures · step + auto
HBM SRAM
05 · Kernels

I/O-Aware Kernels

Why attention is memory-bound, and how FlashAttention tiles + online softmax avoid the k×k matrix.

4 figures · step + auto
draft proposes target verifies ✓✓✓✗ 1 pass
06 · Latency

Speculative Decoding

Draft-then-verify, parallel acceptance, plus EAGLE, Medusa trees and Multi-Token Prediction.

4 figures · step + auto
prefill decode KV transfer →
07 · Scheduling

Prefill-Decode Disaggregation

Chunked prefill to stop interference, and splitting prefill & decode into separate pools.

4 figures · step + auto
GPU HBM CPU DRAM NVMe
08 · Memory

KV Cache Management & Offload

Prefix caching with a radix tree, and offloading cold KV blocks down the memory hierarchy.

4 figures · step + auto
Appendices
pretrain SFT align
A1 · Appendix

Overview of Training

Pretraining → SFT → RLHF/RLAIF, reward models, LoRA, and quantization for cheaper inference.

4 figures · step + auto
SMs / cores memory hierarchy
A2 · Appendix

GPU Hardware

SMs & warps, the register→SRAM→HBM hierarchy, CUDA/ROCm, and writing tiled Triton kernels.

5 figures · step + auto
API sched engine GPU
A3 · Appendix

Inference Runtimes

The serving stack and how vLLM, SGLang, TensorRT-LLM and Triton package every technique above.

4 figures · step + auto